1. Field of the Invention
The present invention relates to a display device and a driving method of a display device, and is applicable to an active matrix type display device based on an organic EL (Electro Luminescence) element, for example. The present invention sets, in advance, a voltage at another terminal of a signal level storage capacitor by a variable reference voltage that falls as a gradation used for display is raised, and thereafter sets a gradation voltage that corresponds to the gradation used for display and which increases as the gradation is raised at one terminal of the signal level storage capacitor, whereby a signal line is driven by a driving signal having a narrow dynamic range, and high luminance is secured.
2. Description of the Related Art
In related art, for a display device using an organic EL element, various devices have been proposed in U.S. Pat. No. 5,684,365, Japanese Patent Laid-Open No. Hei 8-234683, and the like.
FIG. 5 is a block diagram showing a conventional so-called active matrix type display device using an organic EL element. A display unit 2 in the display device 1 is formed by arranging pixels (PX) 3 in the form of a matrix. In addition, the display unit 2 has scanning lines SCN provided in line units in a horizontal direction for the pixels 3 arranged in the form of a matrix, and has signal lines SIG provided in each column so as to be orthogonal to the scanning lines SCN.
As shown in FIG. 6, each pixel 3 is formed by an organic EL element 8, which is a current-driven type self-luminous element, and a driving circuit (hereinafter referred to as a pixel circuit) of each pixel 3 which circuit drives the organic EL element 8.
In the pixel 3, one terminal of a signal level storage capacitor C1 is maintained at a fixed potential, and another terminal of the signal level storage capacitor C1 is connected to a signal line SIG via a transistor TR1 turned on and off by a writing signal WS. Thereby, in the pixel 3, the transistor TR1 is turned on by a rising edge of the writing signal WS, and a potential at the other terminal of the signal level storage capacitor C1 is set to a signal level of the signal line SIG. In timing in which the transistor TR1 is changed from an on state to an off state, the signal level of the signal line SIG is held by the other terminal of the signal level storage capacitor C1.
In the pixel 3, the other terminal of the signal level storage capacitor C1 is connected to the gate of a P-channel type transistor TR2, whose source is connected to a power supply Vcc, and the drain of the transistor TR2 is connected to the anode of the organic EL element 8. In this case, the pixel 3 is set such that the transistor TR2 operates in a saturation region at all times. As a result, the transistor TR2 forms a constant-current circuit supplying a drain-to-source current Ids expressed by the following equation, where Vgs is a gate-to-source voltage of the transistor TR2, μ is mobility, W is a channel width, L is a channel length, Cox is the capacitance of a gate insulating film per unit area, and Vth is a threshold voltage of the transistor TR2. Each pixel 3 thereby drives the organic EL element 8 by a driving current Ids corresponding to the signal level of the signal line SIG which signal level is held by the signal level storage capacitor C1.
                              I          ds                =                              1            2                    ⁢          μ          ⁢                      W            L                    ⁢                                                    C                ox                            ⁡                              (                                                      V                    gs                                    -                                      V                    th                                                  )                                      2                                              (        1        )            
The display device 1 sequentially transfers a predetermined sampling pulse and generates the writing signal WS as a timing signal giving an instruction to write to each pixel 3 by a write scan circuit (WSCN) 4A of a vertical driving circuit 4. In addition, the display device 1 sequentially transfers a predetermined sampling pulse and generates a timing signal by a horizontal selector (HSEL) 5A of a horizontal driving circuit 5. The display device 1 sets each signal line SIG to the signal level of an input signal S1 with the timing signal as a reference. Thereby, on a dot-sequential basis or a line-sequential basis, the display device 1 sets the terminal voltage of the signal level storage capacitor C1 which capacitor is provided in the display unit 2 according to the input signal S1. The display device 1 thus displays an image based on the input signal S1.
As shown in FIG. 7, the organic EL element 8 makes a secular change in current-voltage characteristic in a direction in which a current flows through the organic EL element 8 less easily with use. Incidentally, in FIG. 7, reference L1 indicates an initial characteristic, and reference L2 indicates a characteristic resulting from the secular change. However, when the organic EL element 8 is driven by the P-channel type transistor TR2 in the circuit configuration shown in FIG. 6, the transistor TR2 drives the organic EL element 8 according to a gate-to-source voltage Vgs set according to the signal level of the signal line SIG, whereby change in luminance of each pixel due to the secular change in the current-voltage characteristic can be prevented.
When all transistors forming the pixel circuit, the horizontal driving circuit, and the vertical driving circuit are formed by an N-channel type transistor, these circuits can be produced on an insulating substrate such as a glass substrate or the like by an amorphous silicon process, and thus the display device can be produced easily.
However, as shown in FIG. 8 by contrast with FIG. 6, when each pixel 13 is formed with an N-channel type applied to a transistor TR2, and a display device 11 is formed by a display unit 12 using the pixels 13, the source of the transistor TR2 is connected to an organic EL element 8, and thereby the gate-to-source voltage Vgs of the transistor TR2 is changed due to the change in current-voltage characteristic as shown in FIG. 7. Thus, in this case, a current flowing through the organic EL element 8 gradually decreases with use, and the light emission luminance of the organic EL element 8 gradually decreases. In addition, with the configuration shown in FIG. 8, the light emission luminance varies in each pixel due to variations in characteristic of the transistor TR2. Incidentally, the variations in light emission luminance disturb uniformity on a display screen, and are perceived as nonuniformity or asperity on the display screen.
Thus, forming each pixel as shown in FIG. 9 is conceivable as a device for preventing the decrease in light emission luminance due to the secular change of such an organic EL element and the variations in light emission luminance due to the characteristic variations.
In this case, a display unit 22 in a display device 21 shown in FIG. 9 is formed by arranging pixels 23 in the form of a matrix. In a pixel 23, one terminal of a signal level storage capacitor C1 is connected to the anode of an organic EL element 8. Another terminal of the signal level storage capacitor C1 is connected to a signal line SIG via a transistor TR1 that is turned on and off according to a writing signal WS. Thus, in the pixel 23, voltage at the other terminal of the signal level storage capacitor C1 is set to the signal level of the signal line SIG according to the writing signal WS.
In the pixel 23, the two terminals of the signal level storage capacitor C1 are connected to the source and the gate of a transistor TR2. The drain of the transistor TR2 is connected to a scanning line SCN for power supply. The pixel 23 thereby drives the organic EL element 8 by a transistor TR2 of a source follower circuit configuration whose gate voltage is set to the signal level of the signal line SIG. Incidentally, Vcat in this case is the cathode potential of the organic EL element 8.
The display device 21 outputs the writing signal WS and a driving signal DS for power by a write scan circuit (WSCN) 24A and a drive scan circuit (DSCN) 24B of a vertical driving circuit 24. In addition, the display device 21 outputs a driving signal Ssig to the signal line SIG by a horizontal selector (HSEL) 25A of a horizontal driving circuit 25. The display device 21 thereby controls the operation of the pixel 23.
FIGS. 10A, 10B, 10C, 10D, and 10E are time charts showing the operation of the pixel 23. During an emission period during which the organic EL element 8 emits light, as shown in FIG. 11, the transistor TR1 is set in an off state by the writing signal WS, and the transistor TR2 is supplied with a power supply voltage Vcc by the driving signal DS (FIGS. 10A and 10B). Thereby, in the pixel 23, the gate voltage Vg and the source voltage Vs (FIGS. 10D and 10E) of the transistor TR2 are retained as voltages of the two terminals of the signal level storage capacitor C1. A driving current Ids based on the gate voltage Vg and the source voltage Vs drives the organic EL element 8. Incidentally, this driving current Ids is expressed by Equation (1).
In the pixel 23, when the emission period ends, as shown in FIG. 12, the drain voltage of the transistor TR2 is lowered to a predetermined voltage Vss by the driving signal DS. In this case, the voltage Vss is set to a voltage lower than a voltage obtained by adding the cathode voltage Vcath of the organic EL element 8 to the threshold voltage Vth of the organic EL element 8. Thereby, in the pixel 23, the driving signal DS side of the transistor TR2 for driving functions as a source, the anode voltage (voltage Vs in FIG. 10E) is lowered, and the organic EL element 8 stops emitting light.
At this time, in the pixel 23, as shown by an arrow in FIG. 12, an accumulated charge is discharged from the organic EL element 8 side of the signal level storage capacitor C1. Thereby, the anode voltage of the organic EL element 8 is lowered, and set to the voltage Vss.
Next, in the pixel 23, as shown in FIG. 13, the signal line SIG is lowered to a predetermined voltage Vofs by the driving signal Ssig, and the transistor TR1 is changed to an on state by the writing signal WS (FIGS. 10A and 10C). Thereby, in the pixel 23, the gate voltage Vg of the transistor TR2 is set to the voltage Vofs of the signal line SIG, and the gate-to-source voltage Vgs of the transistor TR2 is set to Vofs−Vss. In this case, letting Vth be the threshold voltage of the transistor TR2, the voltage Vofs is set such that the gate-to-source voltage Vgs (Vofs−Vss) of the transistor TR2 is higher than the threshold voltage Vth of the transistor TR2.
Next, in the pixel 23, for a period indicated by a reference Tth1 in FIGS. 10A to 10E, as shown in FIG. 14, the drain voltage of the transistor TR2 is raised to the power supply voltage Vcc by the driving signal DS with the transistor TR1 retained in an on state. Thereby, in the pixel 23, when a voltage between the terminals of the signal level storage capacitor C1 is higher than the threshold voltage of the transistor TR2, as shown by an arrow in FIG. 14, a charge current flows from the power supply Vcc to the terminal on the organic EL element 8 side of the signal level storage capacitor C1 via the transistor TR2, and the voltage Vs of the terminal on the organic EL element 8 side rises gradually. In this case, an equivalent circuit of the organic EL element 8 is expressed as a parallel circuit of a diode and a capacitance Cel. In this case, a current also flows from the power supply Vcc into the organic EL element 8 via the transistor TR2 in the state shown in FIG. 14. However, unless a voltage between the terminals of the organic EL element 8 exceeds the threshold voltage of the organic EL element 8 due to a rise in source voltage of the transistor TR2, because a leakage current of the organic EL element 8 is considerably smaller than the current of the transistor TR2, the current flowing into the organic EL element 8 is used to charge the signal level storage capacitor C1 and the capacitance Cel of the organic EL element 8. Hence, in the pixel 23, only the source voltage of the transistor TR2 simply rises without the organic EL element 8 emitting light.
In the pixel 23, the transistor TR1 is next changed to an off state by the writing signal WS, and the signal level of the signal line SIG is set to a signal level Vsig indicating the gradation of a corresponding pixel in a next line but one. Thereby, in the pixel 23, the charge current from the power supply Vcc via the transistor TR2 continues flowing to the terminal on the organic EL element 8 side of the signal level storage capacitor C1, and the source voltage Vs of the transistor TR2 continues rising. Also, in this case, the gate voltage Vg of the transistor TR2 rises in such a manner as to follow the voltage rise in the source voltage Vs. Incidentally, the signal level Vsig of the signal line SIG during this period is used to set the gradation of the corresponding pixel in the next line but one.
In the pixel 23, after the passage of a certain time, the signal level of the signal line SIG is changed to the voltage Vofs again. Thus, for a period indicated by a reference Tth2 in FIGS. 10A to 10E, with the potential on the signal line SIG side of the signal level storage capacitor C1 maintained at the voltage Vofs, when the voltage between the terminals of the signal level storage capacitor C1 is higher than the threshold voltage of the transistor TR2, a charge current flows from the power supply Vcc to the terminal on the organic EL element 8 side of the signal level storage capacitor C1 via the transistor TR2, and the source voltage Vs of the transistor TR2 rises gradually. Thereby, as shown in FIG. 15, the source voltage Vs of the transistor TR2 rises gradually such that the gate-to-source voltage Vgs of the transistor TR2 approaches the threshold voltage Vth of the transistor TR2. When the gate-to-source voltage Vgs of the transistor TR2 becomes the threshold voltage Vth of the transistor TR2, the inflow of the charge current via the transistor TR2 stops.
The pixel 23 repeats the process of the inflow of the charge current to the terminal on the organic EL element 8 side of the signal level storage capacitor C1 via the transistor TR2 a sufficient number of times for the gate-to-source voltage Vgs of the transistor TR2 to become the threshold voltage Vth of the transistor TR2 (three times indicated by references Tth1, Tth2, and Tth3 in the example of FIGS. 10A to 10E). Thereby, as shown in FIG. 16, the threshold voltage Vth of the transistor TR2 is set in the signal level storage capacitor C1. Incidentally, the voltages Vofs and Vcat are set such that Vel=Vofs−Vth≦Vcat+Vthel in a state in which the threshold voltage Vth of the transistor TR2 is set in the signal level storage capacitor C1. Thus, the setting is made such that the organic EL element 8 does not emit light. In this case, Vthel is the threshold voltage of the organic EL element 8, and Vel is the voltage of the terminal on the transistor TR2 side of the organic EL element 8.
In the pixel 23, the potential on the signal line SIG side of the signal level storage capacitor C1 is thereafter set to a voltage Vsig indicating the light emission luminance of the organic EL element 8. The voltage indicating the gradation is thus set in the signal level storage capacitor C1 in such a manner as to cancel the threshold voltage Vth of the transistor TR2. Thereby variation in light emission luminance due to variation in threshold voltage Vth of the transistor TR2 is prevented.
Specifically, as shown in FIG. 17, in the pixel 23, after the passage of the period Tth3, the signal level of the signal line SIG is set to a signal level Vsig indicating the light emission luminance of the pixel 23. Next, as shown in a period Tμ, the transistor TR1 is set in an on state by the writing signal WS. Thereby, in the pixel 23, the terminal on the signal line SIG side of the signal level storage capacitor C1 is set to the signal level Vsig of the signal line SIG, a current corresponding to the gate-to-source voltage Vgs as the voltage between the terminals of the signal level storage capacitor C1 flows from the power supply Vcc into the terminal of the organic EL element 8 on the side of the signal level storage capacitor C1 via the transistor TR2, and the source voltage Vs of the transistor TR2 rises gradually.
The current flowing in via the transistor TR2 in this case changes according to the mobility of the transistor TR2. Thereby, as shown in FIG. 18, the source voltage Vs of the transistor TR2 increases rising speed thereof as the mobility of the transistor TR2 is increased. In addition, the current of the transistor TR2 driving the organic EL element 8 increases according to the mobility. In this case, the transistor TR2 of this kind is a polysilicon TFT or the like, and has disadvantages of large variations in threshold voltage Vth and mobility μ.
Thereby, in the pixel 23, for a certain period indicated by the reference Tμ, the transistor TR2 is made to perform an on operation to pass a charge current into the terminal on the organic EL element 8 side of the signal level storage capacitor C1 in a state in which the voltage on the signal line SIG side of the signal level storage capacitor C1 is maintained at the signal level Vsig. The voltage between the terminals of the signal level storage capacitor C1 is thereby lowered by an amount corresponding to the mobility of the transistor TR2. Variation in light emission luminance due to variation in mobility of the transistor TR2 is thus prevented.
In the pixel 23, when the certain period Tμ has passed, the transistor TR1 is turned off by the writing signal WS, so that the signal level Vsig of the signal line SIG is held by the signal level storage capacitor C1, and an emission period begins. Incidentally, it is understood from the above description that the driving signal Ssig of the signal line SIG repeats the signal level Vsig sequentially indicating the gradation of each pixel 23 connected to one signal line with the fixed voltage Vofs inserted between the signal levels Vsig.
The display device of this kind is desired to provide a high yield and high luminance. The yield can be improved by widening a space between pieces of wiring and reducing an area used for a TFT. When this method is used, however, the transistor TR2 driving the organic EL element 8 needs to be miniaturized. As a result, a change in drain current with respect to a change in gate voltage becomes small. It is thus difficult to ensure high luminance.
A conceivable method for solving this problem is to widen the dynamic range of the signal level Vsig indicating the gradation of each pixel and drive the signal line by the driving signal having the wide dynamic range. In this case, however, power consumption increases, and the configuration of the horizontal driving circuit becomes complex.
It is also conceivable that light emission luminance may be heightened by simply lowering the fixed voltage Vofs for threshold voltage correction and thus apparently widening the dynamic range of the gate voltage of the transistor TR2. In this case, however, it is difficult to sink black sufficiently, and contrast is degraded.